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Request for feedback — 5-stage pipelined RISC-V CPU in VHDL — up to Forwarding stage — am I on the right track?

Hello everyone — I’d like to share an update on my project and ask for a bit of guidance from the experts here!

I’m building a fully custom, 5-stage pipelined RISC-V CPU in VHDL — as a personal deep-dive into CPU architecture. So far I’ve implemented up through the Forwarding stage. My next steps will be adding stalling, jump, and branch handling.

In my latest documentation, I’ve included:
✅ Several open questions I’m still exploring
✅ Requests for recommendations on certain architecture trade-offs
✅ Explanations for why I made certain design choices
✅ A walk-through of my debugging techniques (with waveform screenshots)
✅ Notes on how I’m using the Tcl console to help with verification

Here’s my big fear:
Even though things are looking correct so far, I worry that my understanding of some parts (Forwarding, pipeline register structure, control signals) could still be subtly wrong.

If anyone here could take a quick look and let me know if I’m generally on the right track — or if I’ve misunderstood anything — I would be incredibly grateful. I’d love to correct any wrong assumptions before I continue into stalling/jump/branch.

👉 If you have any questions about what I’ve done, feel free to ask — if I don’t know the answer yet, I’ll figure it out!
👉 If you spot misinformation or incorrect assumptions in my design — please tell me! I really want to learn and get this right.

Next steps:
➡️ Implement stalling
➡️ Implement jumping and branching
➡️ Continue refining architecture

Here’s the full project + documentation:
https://lnkd.in/gbCKffPw


https://redd.it/1kzatue
@r_riscv

lnkd.in

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www.tg-me.com/ye/RISC V Reddit/com.r_riscv/3367

8 viewsMay 30 at 21:24

Request for feedback — 5-stage pipelined RISC-V CPU in VHDL — up to Forwarding stage — am I on the right track?

Hello everyone — I’d like to share an update on my project and ask for a bit of guidance from the experts here!

I’m building a fully custom, 5-stage pipelined RISC-V CPU in VHDL — as a personal deep-dive into CPU architecture. So far I’ve implemented up through the Forwarding stage. My next steps will be adding stalling, jump, and branch handling.

In my latest documentation, I’ve included:
✅ Several open questions I’m still exploring
✅ Requests for recommendations on certain architecture trade-offs
✅ Explanations for why I made certain design choices
✅ A walk-through of my debugging techniques (with waveform screenshots)
✅ Notes on how I’m using the Tcl console to help with verification

Here’s my big fear:
Even though things are looking correct so far, I worry that my understanding of some parts (Forwarding, pipeline register structure, control signals) could still be subtly wrong.

If anyone here could take a quick look and let me know if I’m generally on the right track — or if I’ve misunderstood anything — I would be incredibly grateful. I’d love to correct any wrong assumptions before I continue into stalling/jump/branch.

👉 If you have any questions about what I’ve done, feel free to ask — if I don’t know the answer yet, I’ll figure it out!
👉 If you spot misinformation or incorrect assumptions in my design — please tell me! I really want to learn and get this right.

Next steps:
➡️ Implement stalling
➡️ Implement jumping and branching
➡️ Continue refining architecture

Here’s the full project + documentation:
https://lnkd.in/gbCKffPw


https://redd.it/1kzatue
@r_riscv

BY RISC-V Reddit